Medium [CVE-2026-74276] use FIFO occupancy register to determine buffer size

In the Linux kernel, the following vulnerability has been resolved: spi: xilinx: use FIFO occupancy register to determine buffer size The method the driver uses to determine the size of the FIFO has a problem. What it currently does is this: It stops the SPI hardware and writes to the TX FIFO register until TX FIFO FULL asserts in the status register.

But the hardware does not only have the FIFO, it also has a shift register which can hold a byte. This can be seen, when writing a byte to the FIFO (while the SPI hardware is stopped,) the TX FIFO EMPTY is still empty.

So, if we have a FIFO size of 16 for example, the current method returns a 17. This is a problem, at least when using the driver in irq mode.

The same size determined for the TX FIFO is also assumed for the RX FIFO. But it is empty in our case.

So this check spins in a while loop forever locking the driver. This patch fixes the logic to determine the FIFO size.

The driver incorrectly determines the size of its internal buffer, a First-In, First-Out (FIFO) queue. This miscalculation can lead to an overflow when the driver attempts to write more data than the FIFO can hold during a Serial Peripheral Interface (SPI) transaction.

This causes the driver to lose data and enter an infinite loop, resulting in a denial of service (DoS) for the system.